Volume 1

Part I Single Core Processors . . . . . . . . . . . . . . . . . . . . . . .. . .. .1

1 Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . .. .3

2 The Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . .47

3 Architectures for Self-Powered Edge Intelligence . . . . . . .. . .. 89

4 Real-Time Scheduling for Computing Architectures . . . . .. . .. 127

5 Secure Processor Architectures . . . . . . . . . . . . . . . . . . . . .  . . .171

6 Bus and Memory Architectures . . . . . . . . . . . . . . . . . . . . .  . .  201

Part II Application-Specific Processors . . . . . . . . . . . . . . . . . . 213

7 Architectures for Multimedia Processing: A Cross-Layer

Perspective . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..215

8 Post-Quantum Cryptographic Accelerators . . . . . . . . . . . . . . .   237

9 Fault Tolerant Architectures . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277

10 Architectures for Machine Learning . . . . . . . . . . . . . . . . . . . . .321

11 Computer Arithmetic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381

12 Architectures for Scientific Computing . . . . . . . . . . . . . . . . . . .401

Part III Multicore and Reconfigurable Architectures . . . . . . . 415

13 Field-Programmable Gate Array Architecture . . . . . . . . . . . . . 417

14 Coarse-Grained Reconfigurable Array (CGRA) . . . . . . . . . .. . 465

15 Dynamic and Partial Reconfiguration of FPGAs . . . . . . . . . . . 507

16 GPU Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . 531

17 Power Management of Multicore Systems . . . . . . . . . . . . . . . . 561

18 General-Purpose Multicore Architectures . . . . . . . . . . . . . . . . . 595

Volume 2

Part IV Emerging Computing Architectures. . . . . . . . . . . . . . . . 645

19 Compute-in-Memory Architecture . . . . . . . . . . . . . . . . . . . . . . . 647

20 Design Automation Techniques for Microfluidic Biochips . . . . 687

21 Architectures for Quantum Information Processing . . . . . . . . . .723

22 Design and Tool Solutions for Monolithic Three-Dimensional

Integrated Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 751

Part V Processor Design and Programming Flows . . . . . . . . . . . 805

23 Architecture Description Languages . . . . . . . . . . . . . . . . . . . . .. . 807

24 Accelerator Design with High-Level Synthesis . . . . . . . . . . . . . . 841

25 Processor Simulation and Characterization . . . . . . . . . . . . . . . .. . 875

26 Methodologies for Design Space Exploration . . . . . . . . . .  . . .. . 915

27 Virtual Prototyping of Processor-Based Platforms. . . . . . . .  . . . .947

28 FPGA-Specific Compilers . . . . . . . . . . . . . . . . . . . . . . . . . .  . .. .  989

29 Approximate Computing Architectures . . . . . . . . . . . . . . . . . .. . .1027

30 Parallel Programming Models . . . . . . . . . . . . . . . . . . . . . . . . . .. .1069

31 Dataflow Models of Computation for Programming

Heterogeneous Multicores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .1107

32 Retargetable Compilation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  .. .1147

Part VI Test and Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . .  .  1189

33 Verification and Its Role in Design of Modern Computers . . . . . . 1191

34 Bit-Level Model Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  1203

35 High-Level Formal Equivalence . . . . . . . . . . . . . . . . . . . . . . . .. .. 1243

36 Verification of Arithmetic and Datapath Circuits with

Symbolic Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1269

37 Microprocessor Assurance and the Role of Theorem

Proving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . 1321

38 Versatile Binary-Level Concolic Testing . . . . . . . . . . . . . . . . . .. . . 1365

39 Information Flow Verification . . . . . . . . . . . . . . . . . . . . . . . . .  . . . 1389

40 Verification of Quantum Circuits . . . . . . . . . . . . . . . . . . . . . . .. . . . 1413

Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . 1441

 This handbook presents the key topics in the area of computer architecture covering from the basic to the most advanced topics, including software and hardware design methodologies. It will provide readers with the most comprehensive updated reference information covering applications in single core processors, multicore processors, application-specific processors, reconfigurable architectures, emerging computing architectures, processor design and programming flows, test and verification. This information benefits the readers as a full and quick technical reference with a high-level review of computer architecture technology, detailed technical descriptions and the latest practical applications.

 The content is spread over multiple sections, and in each section, specific chapters offer a detailed glimpse of a topic of interest. The chapters are presented in increasing order of advanced concepts. It is also cross-linked in such a manner that reader can peruse a chapter with only necessary pre-requisite from selected, prior chapters.

 In the first section of single-core processors, three chapters provide the background of computer organization, microarchitecture, and communication networks. This is complemented with chapters on operating systems, edge computing, and secure computing architectures – which provide sufficient foundation for a reader to move toward more advanced notions in any of the following sections.

 The section on application-specific processors provides valuable insights into the growing demands from application developers to have customized architectures, also referred to as co-processors or accelerators. From a wide range of application segments, multimedia processing, scientific computing, machine learning, and cryptographic workloads are chosen to be covered here. Since these applications heavily depend on digital arithmetic, a short overview of the concepts is presented as well. Multimedia, machine learning, and several other domain-specific architectures are known to get influenced – for good or worse – due to the device-level faults appearing in advanced technology nodes. This is discussed in the section of fault-tolerant architectures.

 Various application-specific processors and general-purpose ones come together to contribute in the rich tapestry of modern System-on-Chips (SoCs). This also enhances the notion of architectures significantly by offering reconfigurability as a property. Multicore SoCs and reconfigurable architectures are studied in a dedicated section, covering general-purpose multicore architectures, Graphics Processing Units (GPUs), and Field Programmable Gate Arrays (FPGAs). Furthermore, readers are offered to delve into the Coarse-Grained Reconfigurable Architectures (CGRAs), dynamic and partial reconfigurability notions as well as power management challenges for multicore systems.

Growing technology prowess offers various capabilities to modern architects. In the section of Emerging Computing Architectures, these are studied, including compute-in-memory architectures, architectures for microfluidic biochips, Quantum computing, and the ones benefitting from 3D ICs. The complexity of modern computer architectures can only be managed with the help of powerful design automation flows. This is discussed in the section on Processor Design and Programming Flows. The introductory chapters on parallel programming models and dataflow models help reader to familiarize with the abstract notions necessary to grasp the design automation concepts. This foundation brings further the methodologies for design space exploration, followed by specific tool-flows, as elaborated in the chapters on architecture description languages, high-level synthesis, processor simulation, and virtual prototyping. For customizable, application-specific, and reconfigurable architectures, the compilation flows present a critical role to extract maximum efficiency out of the computing fabric. These are discussed in two chapters on FPGA-specific compilers and retargetable compilers. Balancing of technology constraints all the way to the application layer is a complex design automation challenge, which is discussed in the chapter on approximate computing architectures.

 The last section of this volume brings forth the classic and modern techniques for testing and verification of computer architectures.